View ICS91719_867039.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS91719
Low EMI, Spread Modulating, Clock Generator
Features: * ICS91719 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications. Generates an EMI optimized clock signal (EMI peak reduction of 714 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. * ICS91719 focuses on the lower input frequency range of 14.318 to 80.00 MHz with a spread modulation of 20kHz to 40kHz. Specifications: * Supply Voltages: VDD = 3.3V 0.3V * Frequency range: 14.318 MHz Fin 80 MHz * Cyc to Cyc jitter: <150ps * Output duty cycle 40/60% (worst case) * Guarantees +85C operational condition. * 16-pin TSSOP package 4.4mm body (173mils), 0.65 mm pitch * 14.318 MHz crystal input or reference clock input * 27MHz, 48MHz and 66MHz reference clock input
Pin Configuration
GND X1 _CLKIN X2 GNDA VDDA VDD GND * * CLKOUT/FS_IN0
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDDREF VDDREF_SEL_2.5V/3.3V# ^ REF_OUT/VDDREF_SEL_1.8V * * **REF_Stop ^PD# SCLK SDATA ^SPREAD_ENABLE/FS_IN1
16-pin TSSOP
Notes: ** Internal pull-down ^ Internal pull-up
Input Select Functionality FS_IN1 FS_IN0 MHZ
0 0 1 1 0 1 0 1 14.318 in 27.00 out 14.318 in/out 27.00 in/out 48.00 in/out 66.66 in/out
Default Spread %
-0.8% downspread -0.8% downspread -0.8% downspread -0.8% downspread
Block Diagram
REFOUT CLKIN PLL1 Spread Spectrum Spectrum CLKOUT CLKOUT
REF Voltage Select Functionality
Pin14
0 0 1 1
Pin15
0 1 0 1
REF Voltage
N/A 1.8V 2.5V 3.3V
SPREAD# PD# REF_STOP SDAT SD A SCLK FS_IN0:1
Control Logic Config. Reg.
0506D--08/16/04
ICS91719
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME GND X1 _CLKIN X2 GNDA VDDA VDD GND CLKOUT FS_IN0 ^SPREAD_ENABLE FS_IN1 SDATA SCLK ^PD# **REF_Stop REF_OUT/VDDREF_SEL_1.8V * * VDDREF_SEL_2.5V/3.3V# ^ VDDREF PIN TYPE PWR IN OUT PWR PWR PWR PWR OUT IN IN IN IN IN IN IN/OUT PWR PWR DESCRIPTION Ground pin for 3V outputs Crystal input or CLOCKIN input Crystal output Analog ground Analog power supply for 3V Power supply for 3V Ground pin for 3V outputs Modulated clock output Latched input for input frequency select Spread enable pin Latched input for input frequency select Data pin for I2C circuitry 5V tolerant Clock pin for I2C circuitry 5V tolerant Power down Stop control for REF_CLOCK output STOP:1, RUNNING:0 REF_CLOCK output REF_CLOCK power supply voltage select Power supply for REF_CLOCK
^internal pull-up **internal pull-down
0506D--08/16/04
2
ICS91719
Table 1: Frequency Configuration Table (See I2C Byte 0)
FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd %
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DOWN 1 0 1 SPREAD (-) 0 1 Center 0 1 Spread (+/-) 0 1 0 DOWN 1 0 SPREAD 1 (-) 0 1 0 1 0 1 CENTER 0 SPREAD 1 (+/-) 0 1 0 DOWN 1 0 1 SPREAD (-) 0 1 Center 0 1 Spread (+/-) 0.60 0.80 1.00 1.25 1.50 2.00 0.50 1.00 0.60 0.80 1.00 1.25 1.50 1.75 2.00 2.50 3.00 0.30 0.40 0.50 0.70 1.00 1.20 1.50 0.60 0.80 1.00 1.25 1.50 2.00 0.50 1.00
14in/27out
14in/14ou t 27in/27ou t
48in/48ou t 66in/66ou t
0506D--08/16/04
3
ICS91719
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
* * * * * * * * * * (host) sends a start bit. (host) sends the write address D2 (H) will acknowledge (host) sends a dummy command code will acknowledge (host) sends a dummy byte count will acknowledge (host) starts sending first byte (Byte 0) through byte 6 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
Controller Controller ICS clock Controller ICS clock Controller ICS clock Controller
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK
ACK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
0506D--08/16/04
4
ICS91719
Byte 0:
TYPE BYTE
0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Affected Pin Pin # Name
FS0 FS1 FS2 FS3 FS4 PD# Tri_Sate Spread Enable
Control Function
Spread/FS0 Spread/FS1 Spread/FS2 Spread/FS3 FS4 PD# Tri_Sate Spread Enable Spread Spectrum Control FS 3:4 Hard/Software Select
Bit Control 0 1
PWD
RW RW RW R R/R W RW RW
1 0 0 0 0 1 1
Hi-Z OFF
LOW ON
Bit 0
HW/SW Control
RW
HW
SW
0
Byte 1:
TYPE BYTE
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Affected Pin Name
Reserved SLEW FS-IN_1 Readback FS-IN_0 Readback SLEW CLK_OUT_Enable REF_OUT_Enable Reserved
Control Function
Reserved Slew Rate REF-OUT FS-IN_1 Readback FS-IN_0 Readback Slew Rate CLK-OUT CLK_OUT_Enable REF_OUT_Enable Reserved
Bit Control 0 1
PWD
R RW Nominal Fast Not RW Freerun Freerun RW Nominal Fast RW Nominal Fast RW Disable Enable RW Disable Enable R -
1 1 1 1 1 1 1 1
Byte 2:
TYPE BYTE
2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Affected Pin Pin # Name
x x x x x x x x RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Bit Control 0 1
Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable
PWD
RW RW RW RW RW RW RW
1 1 1 1 1 1 1 1
0506D--08/16/04
5
ICS91719
Byte 3:
TYPE BYTE
3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
X
Affected Pin Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Bit Control 0 1
PWD
X X X x X X
X
RW Disable Enable RW Disable Enable Not RW Freerun Freerun Not RW Freerun Freerun Not RW Freerun Freerun RW Disable Enable RW Disable Enable RW Disable Enable
1 1 1 1 1 1 1 1
Byte 4:
TYPE BYTE
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
X X X X X X X X
Affected Pin Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Bit Control 0 1
Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable
PWD
RW RW RW RW RW RW RW RW
1 1 1 1 1 1 1 1
Byte 5:
TYPE BYTE
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
X X X X X X X X
Affected Pin Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Bit Control 0 1
Disable Disable Disable Disable Enable Enable Enable Enable
PWD
RW RW RW RW
1 1 1 1 1 1 1 1
0506D--08/16/04
6
ICS91719
Byte 6:
TYPE BYTE
6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
X X X X X X X X
Affected Pin Name
Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
Control Function
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Bit Control 0 1
-
PWD
R R R R R R R R
1 1 1 1 1 1 1 1
0506D--08/16/04
7
ICS91719
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Voltage on any pin with respect to GND . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . Operating Temperature . . . . . . . . . . . . . . . . . . Ambient Operating Temperature under Bias . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 3.3 V -0.5 to +7.0 V -55C to +125C 0C to +85C -55 to +125 C 0.5 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 85C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Powerdown Current Input Frequency Input Crystal Frequency Input Clock Frequency Pin Inductance Input Capacitance1 SYMBOL V IH V IL I IH I IL1 I DD3.3PD Fi F CY I F CLK I Lpin C IN C OUT C INX Ttrans Ts T STAB t PZH,t PZL CONDITIONS MIN 2 V SS - 0.3 -5 -5 TYP MAX V DD + 0.3 0.8 5 UNITS V V mA mA mA MHz MHz MHz nH pF pF pF ms ms ms ns
V IN = V DD V IN = 0 V; Inputs with no pull-up resistors
V DD = 3.3 V
Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From V DD = 3.3 V to 1% target frequency Output enable delay (all outputs)
27
3 5 14.318 14.318 Typ + 10% 80 7 5 6 36 45 3 3 3 10
Transition time 1 Settling time1 Clk Stabilization 1 Delay 1
1
1 1
Guaranteed by design, not 100% tested in production.
0506D--08/16/04
8
ICS91719
Electrical Characteristics - CPU
TA = 0 - 85C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH3 IOH = -1 mA Output Low Voltage VOL3 IOL = 1 mA Rise Time tr3 VOL = 0.41V, VOH = 0.86V Fall Time tf3 VOH = 0.86V VOL = 0.41V measurement from differential waveform dt3 Duty Cycle 0.35V to +035V VT = 50% tjcyc-cyc1 Jitter, Cycle to cycle
1 2
MIN 2.4 0.5 0.5 45
TYP
MAX 0.4 1 1 55 150
UNITS V ns ns % ps
0.7 0.8 51 76
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF
TA = 0 - 85C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH1 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 Duty Cycle Jitter
1
MIN 20 2.4 -29 29 1 1 45
TYP 48
MAX 60 0.4 -23 27 2 2 55 300
1.25 1.3 53 170
UNITS MHz V V mA mA ns ns % ps
dt11 tjcyc-cyc1
VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0506D--08/16/04
9
ICS91719
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 16 D mm. MIN 4.90 MAX 5.10 MIN .193 D (inch) MAX .201
-Ce
b SEATING PLANE
aaa C
Reference Doc.: JEDEC Publication 95, MO-153 10-0035
4.40mm Body, .65mm pitch
Ordering Information
ICS91719yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0506D--08/16/04
10

▲Up To Search▲

Price & Availability of ICS91719

	To Download ICS91719 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .